This invention generally relates to a multipurpose interface circuit for use to interface one communication bus to another. More specifically, the present invention is in the form of a PC card that provides interface between a computer bus such as that of a general purpose computer and a command/response, time division multiplexing data bus such as, for example, a MIL-STD-1553 bus. This military standard contains requirements for aircraft internal command/response, time division multiplexing data bus techniques utilized in systems integration of aircraft subsystems. This MIL-STD applies to a variety of avionics applications including, for example, the F-15. The multipurpose interface of the present invention is particularly adapted for use with data buses where this MIL-STD applies, but more generally may also be adapted for use to interface other data buses as well. For purposes of explaining the features and advantages of the invention and its preferred embodiment, the invention will be described with reference to its application with a MIL-STD-1553 bus. It is to be understood that the version of MIL-STD-1553 being referred to throughout is the most current version as of the filing of this application.
The multipurpose interface of the present invention provides a host computer, such as a microcomputer, with a capacity of communicating on a MIL-STD-1553 avionics multiplex bus or the like. This allows the host computer to be used to emulate avionics for the purpose of simulation or testing. The invention provides an intelligent interface. It handles all of the communication protocol per the MIL-STD-1553 specification. 64K bytes of on-board RAM are used for all communication to and from the interface. It includes a modular memory mapped design allowing the PC card to be modified for use with different microcomputer bus systems, such as those known as the Multibus I, Multibus II, and Q-Bus Systems. The interface of the present invention functions in several modes: a bus controller mode, a remote terminal mode, a bus monitor mode, and a bus analyzer mode. In the bus controller mode the interface functions to provide the host computer with the capability of simulating the controller of a typical avionics bus. It is capable of handling all of the scheduling of the mux messages without intervention from the processor of the host computer. In the remote terminal mode the interface functions to provide the host computer with the capability to simulate any or all of the remote terminals of a typical avionics bus. In the monitor mode the interface functions to provide the host computer with the capability of monitoring the operation of any or all of the remote terminals. In the bus analyzer mode the interface functions to provide the host computer with the capability of taking a "snap shot" of the bus, thus giving an analysis of bus traffic versus time. In the bus analyzer mode bus traffic may be conditionally traced by a remote terminal address and/or subaddress. Using an on-board co-processor, the analyzer mode provides a message trapping capability similar to a logic analyzer.
The interface of this invention generally comprises a main controller which includes a 16-bit controller and a firmware microstore in the form of PROM which contains the software for the controller. The main controller primarily handles input/output functions and controls the transfer of data to and from the 1553 Bus into a shared RAM memory. The software stored in the microstore controls how the data is handled and interpreted making it easier to modify the controller's operation to accommodate its use with different bus standards and data protocols/formats. The interface also includes a co-processor which has direct access to the shared RAM. The main controller primarily handles input/output functions, while data processing is primarily handled by the co-processor. By using the on-board co-processor within the interface PC card, a greater number of interface PC cards of the present invention may be used with a single host computer.
The interface of the present invention also includes an interface module that formats and protocols data from the RAM as appropriate for the bus protocol and format of the host computer.
There are other known interface devices for use in providing interface between buses including a MIL-STD-1553 bus. These other known devices also are believed to operate in the various modes identified above. However, it is believed that the interface of the present invention has novel advantages over these other devices.
As mentioned previously, the interface of the present invention is an intelligent interface. Its modular memory mapped design allows the card to be modified to different microcomputers systems including the Multibus I, Multibus II, and Q-Bus Systems. Different derivatives of the 1553 specification can be accommodated with firmware changes. The timing requirements of all specifications including MIL-STD-1553A and McAir A3818 can be satisfied. Hence the interface of the present invention provides substantial versatility by making firmware and software as opposed to hardware changes.
In the bus controller mode the interface card is capable of scheduling bus traffic per the mux specifications without host processor intervention making sophisticated bus controller simulation possible. In the remote terminal and monitor modes the card can simulate or monitor any combination of remote terminals. For example, one or more terminals can be simulated while monitoring any or all of the remaining terminals. In the bus analyzer mode mux data can be conditionally collected according to remote terminal address and subaddress. This allows only the data of interest to be collected. Complex trigger conditions can be set up to stop data collection on certain events making the card a true mux analyzer. Messages are also time-tagged providing timing information. Another advantage of the interface of the present invention is that the on-board co-processor can be programmed to perform a wide range of user required processing of data or controlling of the mux interface. The co-processor software performs bus controller scheduling and bus analyzer triggering. In addition, the interface module for the host computer does not require that the interface card operate as a bus master. This simplifies modification for use with any system bus. The on-board memory also allows use of as many interfaces of this invention as needed for operation in a single host computer system without bus contention problems.
These and other advantages of the invention are apparent from the additional description to follow: